different result when compiling asram.v with quartus ii v9.1 and quartus ii v10.1

What do you want to achieve? This is a RAM simulation model, not suited for synthesis.

P.S.: Apart from the fact, that your design is effectively unsynthesizable Verilog, the different compilation behaviour should be explained. There's something strange in Quartus 10 and 11. If you look to the RTL netlist, two instances of ASYNC_RAM are inferred from the code. I'm not sure, if the asynchronous RAM block is a new feature in Quartus, but it's not supported by any recent FPGA and silently discarded in the Quartus 10/11 synthesis.

If you disable Auto RAM Replacement in the Quartus synthesis options, you get the RAM synthesized in logic cells as in Quartus 9.

A huge number of unsafe latch behaviour warnings is telling you, that the design isn't synthesizable.