Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

different result when compiling asram.v with quartus ii v9.1 and quartus ii v10.1

I want to compile the verilog source code of one async ram. The code shows below: module asram(a,io,ce_,oe_,we_,lb_,ub_); parameter dqbits=16; parameter memdepth=255; parameter addbits=7; ...