Different phases in PLL

If you are interested in finding out the clock distribution delay, you should avoid taking the PLL clock outputs straight to pin as that may introduce unrelated routing delay.

You can try the following circuit:

Have a TFF feed DFF then drive out to an output pin. Use each clock output of PLL to feed each set of TFF and DFF. TCO of this circuit will be the sum of input clock delay + PLL offset + PLL clock tree to IO cell delay + IO cell output register to pin delay.

BTW, you need enable fast output register on DFF so that they go into IO cell. You may also have to enable other options to make sure DFF doesn't get synthesized away.

In order to get relevant comparison, you should make sure your output pins are adjacent to each other and in the same IO bank. You should also note that the clock delay to IO cell register may be different than that of a core register.