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Altera_Forum
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16 years ago

Different compiling results ModelSim <-> Quartus 9.0

Hi, I have a VHDL Design containing a case statement. If I compile this design with QuartusII 9.0 I get no error; compiling this design in ModelSim Altera Starter Edition I get some errors lik...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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I Think the reason is that I use a "generic expression" in the case-statement.

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Right. The solution is to avoid them for designs intended for ModelSim simulation. There are also some other cases where some expressions are tolerated with Quartus integrated synthesis but complained by ModelSim. According to the VHDL standard, only simple expressions are allowed in a case choices term. A shift operation isn't a simple expression. I guess, the best readable replacement is a chain of if then elsif.