library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity VERSION_REGISTER is
	generic(CPLD_VER: NATURAL:= 0;
			HW_VER	: NATURAL:= 2;
			HW_TYPE	: NATURAL:= 3;
			MAX_CS_LINES: POSITIVE:= 16;-- max generated CS-Lines in complete design
			START_CS_NR	: NATURAL:= 0);-- CS-Line number of first version-register
	port(CS				: in BIT_VECTOR((MAX_CS_LINES-1) downto 0);
		 nRD			: in STD_LOGIC;
		 DATA			: out STD_LOGIC_VECTOR(7 downto 0));
end VERSION_REGISTER;

architecture BEHAVIOR of VERSION_REGISTER is
begin
	
	process(CS, nRD)
		variable ZERO			: BIT_VECTOR((MAX_CS_LINES-1) downto 0):=(others=>'0');-- zero vector of length MAX_CS_LINES
		variable SHIFT_PATTERN	: BIT_VECTOR((MAX_CS_LINES-1) downto 0):=(0=>'1',others=>'0');-- pattern of length MAX_CS_LINES all zero but Bit0=1
	begin
		
		if (CS = ZERO) then -- if no CS for CPLD active, set Databus to high Z
			DATA <= (others =>'Z');
		elsif (nRD'EVENT and nRD='0') then
			case CS is
					when (SHIFT_PATTERN sll START_CS_NR) 	 => DATA <= CONV_STD_LOGIC_VECTOR(CPLD_VER, 8);--CPLD version register
					when (SHIFT_PATTERN sll (START_CS_NR +1))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_VER, 8);--HW version register
					when (SHIFT_PATTERN sll (START_CS_NR +2))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_TYPE, 8);--HW type register
					when others => DATA <= (others =>'Z');
			end case;
		end if;	
		
	end process;	

end BEHAVIOR;