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Altera_Forum
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11 years ago

Difference Equation in VHDL

Hello, I am using the kit DE0 - Nano that has a EP4CE22F17C6N FPGA, to control a multilevel converter. The code that I made works in open loop, showing that the PWMs channels are working. The code to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Here is a map of your nodes:

((senoComp - ValorAtual)*9) => EK => EK1 => EK2

k0*UK1 + k1*UK2 + k2*EK - k3* EK1 + k4*Ek2 => UK => UK1 => Uk2

all above are variables and hence wired directly, there might be some registers implied but too complicated to work out.

what is your original difference equation?

do not use variables, use signals so we can follow you.

do not multiply five times/add/subtract without pipelining.

do not divide by 1000 if you can, e.g. scale to 1024 then discard 10 lsbs.