Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- I am a newbie to FPGA programming and VHDL. I just know the basics. I was wondering if someone could tell me the difference between: unisgned(a,b) and to_unsigned(a,b) --- Quote End --- Your first statement is not correct VHDL. They are both type conversion procedures. Here's a couple of examples
Cheers, Dave-- A standard-logic vector, where bits mean anything signal slv : std_logic_vector(7 downto 0) := X"0F"; -- An unsigned integer, where bits mean positive numbers, eg., 0->255 signal u : unsigned(7 downto 0) := X"0F"; -- Conversion of std_logic_vector to unsigned u <= unsigned(slv); -- Conversion of unsigned to std_logic_vector slv <= std_logic_vector(u); -- Conversion of an integer to unsigned of width 8-bits u <= to_unsigned(123, 8); -- Conversion of an integer to std_logic_vector slv <= std_logic_vector(to_unsigned(123, 8)); - Altera_Forum
Honored Contributor
unsigned(a) - note: not (a,b) - is a type conversion of a similar type a (ie. another array of std_logic, like signed or std_logic_vector.
to_unsigned(a,b) converts an integer a to an unsigned type with length b. - Altera_Forum
Honored Contributor
Could you please explain this line of code:
constant ADR_CTRL : unsigned(ADDRESS_WIDTH - 1 downto 0) := to_unsigned(CTRL_OFF, ADDRESS_WIDTH); - Altera_Forum
Honored Contributor
its just a constant with the value CTRL_OFF, with the width ADDRESS_WIDTH. It is an unsigned number
- Altera_Forum
Honored Contributor
Thanks a lot tricky and dave