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Altera_Forum
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13 years ago

Difference between unisgned(a,b) and to_unsigned(a,b)?

Hey guys,

I am a newbie to FPGA programming and VHDL. I just know the basics. I was wondering if someone could tell me the difference between:

unisgned(a,b) and to_unsigned(a,b)

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I am a newbie to FPGA programming and VHDL. I just know the basics. I was wondering if someone could tell me the difference between:

    unisgned(a,b) and to_unsigned(a,b)

    --- Quote End ---

    Your first statement is not correct VHDL.

    They are both type conversion procedures. Here's a couple of examples

    
    -- A standard-logic vector, where bits mean anything
    signal slv : std_logic_vector(7 downto 0) := X"0F";
    -- An unsigned integer, where bits mean positive numbers, eg., 0->255
    signal u : unsigned(7 downto 0) := X"0F";
    -- Conversion of std_logic_vector to unsigned
    u <= unsigned(slv);
    -- Conversion of unsigned to std_logic_vector
    slv <= std_logic_vector(u);
    -- Conversion of an integer to unsigned of width 8-bits
    u <= to_unsigned(123, 8);
    -- Conversion of an integer to std_logic_vector
    slv <= std_logic_vector(to_unsigned(123, 8));
    

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    unsigned(a) - note: not (a,b) - is a type conversion of a similar type a (ie. another array of std_logic, like signed or std_logic_vector.

    to_unsigned(a,b) converts an integer a to an unsigned type with length b.
  • Altera_Forum's avatar
    Altera_Forum
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    Could you please explain this line of code:

    constant ADR_CTRL : unsigned(ADDRESS_WIDTH - 1 downto 0) := to_unsigned(CTRL_OFF, ADDRESS_WIDTH);
  • Altera_Forum's avatar
    Altera_Forum
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    its just a constant with the value CTRL_OFF, with the width ADDRESS_WIDTH. It is an unsigned number