Difference between unisgned(a,b) and to_unsigned(a,b)?

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I am a newbie to FPGA programming and VHDL. I just know the basics. I was wondering if someone could tell me the difference between:

unisgned(a,b) and to_unsigned(a,b)

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Your first statement is not correct VHDL.

They are both type conversion procedures. Here's a couple of examples

-- A standard-logic vector, where bits mean anything
signal slv : std_logic_vector(7 downto 0) := X"0F";
-- An unsigned integer, where bits mean positive numbers, eg., 0->255
signal u : unsigned(7 downto 0) := X"0F";
-- Conversion of std_logic_vector to unsigned
u <= unsigned(slv);
-- Conversion of unsigned to std_logic_vector
slv <= std_logic_vector(u);
-- Conversion of an integer to unsigned of width 8-bits
u <= to_unsigned(123, 8);
-- Conversion of an integer to std_logic_vector
slv <= std_logic_vector(to_unsigned(123, 8));

Cheers,

Dave