Diagnosing "signal was determined to be a clock .." message.

If it pointed back to the code, it would just point to the signal that it mentions. What you wanted to know is where that is used as a clock. Of course, that's more difficult since it could be thousands of locations(for cases where someone forgot to assign something that really isn't a clock), and in those cases it still might not be clear. Some quick ideas:

1) Put a clock assignment on it. Something simple like "create_clock -name bad_clk -period 10.0 <nodename>". So now it has a clock on it(and all clocks are related by TimeQuest). Rerun timing analysis and report_timing -to bad_clk, as well as do a report_timing -from bad_clk. Your going to see the exact nodes that use that as a clock.

2) Go to the Fitter Report and look at the Control Signals section. Sort on usage and scroll down to where all the clocks are. Note that this list has nothing to do with your TimeQuest constraint, but is a list of every physical node that directly drives the .clk port of a regsiter. Most of them should be PLLs or input ports and make sense. If something doesn't make sense, go look at it. Even if it's not this reset issue, this isn't a bad thing to do anyway...