--- Quote Start ---
Have you tried "not a clk" option in assignment editor.
--- Quote End ---
That's a useful hint, thanks, although in this case setting "not a clock" would only have covered up the problem.
--- Quote Start ---
the only connection with clk is that master reset will be lobal to avoid delay and clock slip at release unless somebody connected it by mistake.
--- Quote End ---
A few minutes ago I found the cause while looking into another fault. It was a mistake, the author had set a register to the value of another signal during reset rather than to a fixed value so it was inferring a latch, passing the value through while reset was active, even though the preceding source was itself reset.
proc_a : process(rst,clk)
begin
if (rst='1') then
sig_a <= '0' ;
elsif rising_edge(clk) then
if (enable_a = '1') then
sig_a <= sig_in ;
end if;
end if;
end process proc_a ;
proc_b : process(rst,clk)
begin
if (rst='1') then
sig_b <= sig_a ;
elsif rising_edge(clk) then
if (enable_b = '1') then
sig_b <= sig_a ;
end if;
end if;
end process proc_b ;
Changing the second process to the following corrected the error without changing the behaviour:
if (rst='1') then
sig_b <= '0' ;
elsif rising_edge(clk) then
Although I have now resolved this particular instance, it would still be useful to know if there is a way to get TimeQuest or Quartus to identify the process which was causing the warning message.
Honored Contributor
