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I don't understand why the statement: "VHDL has memory" is the answer.
Because when this design starts and rst!='1', pre!=1 or ce!=1, than q is undefined. It didn't have a value yet and now it still doesn't have a defined value. This would mean there is something undefined going to happen, right?
Thats how I've understood it, since we made a mistake a few times by not always defining the output. We tought everything was right, but it wasn't working. Than we added a last else statement and it worked.
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I think you're right. If first rising edge is not coming then q would be U.
Honored Contributor
