Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

DFF with clock enable

Hello everyone, I was wondering, when implementing a DFF with clock enable : library IEEE; use IEEE.STD_LOGIC_1164.all; entity D_FF_VHDL is port ( clk : in std_logic; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Undefined my and it hasn t been assigned a value yet. It wont have a value without a clock edge. If ce is 1 and q is still u after rising edge, make sure d has a value.