DFF with clock enable

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Hello everyone,

I was wondering, when implementing a DFF with clock enable :

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity D_FF_VHDL is

port

( clk : in std_logic; rst : in std_logic; pre : in std_logic; ce : in std_logic; d : in std_logic; q : out std_logic )

;end entity D_FF_VHDL;

architecture Behavioral of D_FF_VHDL is

begin

process (clk) is

begin

if rising_edge(clk) then

if (rst='1') then

q <= '0';

elsif (pre='1') then

q <= '1';

elsif (ce='1') then

q <= d;

end if;

end if;

end process;

end architecture Behavioral;

What happens with q when ce equals to '0'? How does the FF keeps last state? Why after q<=d line shouldn't we add :

else

q<=q?

As I understand there shouldn't be any state at which q is unknown. Hence, when the clock is rising but disabled by ce='0' state of q in unknown.

Please explain.

Much appreciated,

Boris.

Simulation Results[/B][/B]

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you can add that line if you wish but it is implied that if a condition is not defined it means it saves its last value.