Honored Contributor
Honored ContributorYes, there are definite differences between working with ASICs and FPGAs. I need to educate myself on the proper use of clock drivers in an FPGA, but it is actually fairly similar to that of an ASIC. For the ASIC that I just worked on, there were many clock domains, and I would need quite a few global resources if this design was implemented in an FPGA, and would definitely need to use a Stratix II or Stratix III, if anything so I could do temperature and voltage variations in my timing analysis. It really is weird that I can't do that using the Stratix family.....just doesn't make sense to me why Altera left this out.
I just completed a new Name Finder run, and this time using get_pins with the compatibility mode box checked, this was returned: inst20|inst2|i2c_clk|regout Yes, you're right that I'm used to using get_pins, and that commnand seems to be more universal.
