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Altera_Forum
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18 years ago

Determining path for cell in netlist

Hi, I'm trying to apply a generated clock to a clock net burried in the hieracrchy, like so: create_generated_clock -name {oven_ctl_i2c_clk} -divide_by 1024 -source [get_ports {osc_clk0}] ...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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I'm used to assigning a generated clock directly to the Q pin of a flop...

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Are you used to doing this in an ASIC? Avoid doing it in an FPGA. It is better to drive the clock with a PLL or to use a clock enable.

If you do drive a clock with a register or any other logic, be aware of the caveats in my posts at http://www.alteraforum.com/forum/showthread.php?t=754.