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Altera_Forum's avatar
Altera_Forum
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18 years ago

Determining path for cell in netlist

Hi, I'm trying to apply a generated clock to a clock net burried in the hieracrchy, like so: create_generated_clock -name {oven_ctl_i2c_clk} -divide_by 1024 -source [get_ports {osc_clk0}] ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Name Finder will only return a list of items if I use the get_keepers function; get_pins returns an empty list.

I believe if I want to apply the generated clock to the Q pin of the divide flop, I would use this (I think...):

[get_nodes inst20|inst2|i2c_clk|regout]

This appears to place the generated clock on the Q output of the DFF in the cell i2c_clk, but it's not too clear based on that the Technology Map Viewer shows. However, based on what the TimeQuest documentation says, I believe using get_keepers will accomplish the same result.

If anyone can correct me on this, please let me know!

Thanks...