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Altera_Forum
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18 years ago

Determining path for cell in netlist

Hi, I'm trying to apply a generated clock to a clock net burried in the hieracrchy, like so: create_generated_clock -name {oven_ctl_i2c_clk} -divide_by 1024 -source [get_ports {osc_clk0}] ...
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Altera_Forum
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18 years ago

Brad,

Thanks for the reply....

The only way that I can return a non-empty list is by using get_keepers, which appears to return a list of nets (?), but I'm not sure what they are. I'm used to assigning a generated clock directly to the Q pin of a flop, but so far, I haven't been able to determine how that is done with the Altera toolset.

Tony