Honored Contributor
Honored ContributorDefinitely Learn one or the other:
Verilog is very easy to learn if you have any basic programming experience. But like C, you can shoot yourself in the foot with it. (IE, it's easier to read, but will allow you to do things that will not always work). VHDL is more structured, so it's a bit harder to read at first, and has more typing to get something done. Verilog is mainly using in the commercial industry in the US. VHDL tends to be mainly used in military industry or Europe. Both are valid and good hardware description languages, that are well worth the time to learn. You will see both in time. The advantage these have over schematic is many, but mainly the complexity of the designs you can easily accomplish. Pete
