Honored ContributorIs there a way to specify a design entirely by hand without Quartus? I am asking because my research project on asynchronous circuits requires full control of wiring and logic gate placement. Furthermore, Quartus sometimes crashes for asynchronous designs (see for example: http://www.altera.com/support/kdb/solutions/rd09232013_776.html)
Thanks!
Honored ContributorAs far as I know asynchronous design is not recommended for FPGAs....
Honored ContributorYou can use WYSIWYG primitives instead of synthesis and you can use routing constraint files to specify place and routing.
The documentation is, AFAIK, between poor and non-existant but it's possible.Honored ContributorThanks! This could be the way to go for me. I need to look into this more.
But with this, I would still use Quartus, right? I would just constrain it in every aspect (wiring and logic gate placement)? Do you know, how I would turn off synthesis and fitting in Quartus, then?Honored ContributorYou can bypass synthesis and fitting by providing your own Verilog/VHDL netlist with WYSWIG primitives.
But you must use Quartus for place and route.
