Design works with Quartus Prime Lite v15.1.0, but not with Quartus Prime Lite v17.0.2

Hello,

I have a design with a custom QSPI communication link between a TI DSP processor and a MAX 10 FPGA. The design was tested to work consistently with valid data exchange when the FPGA code is compiled using Quartus Prime Lite v15.1.0.

We purchased the Intel Functional Safety Data Package and so we would like to migrate to Quartus Prime Lite v17.0.2, since it is the latest qualified version for the FSDP. We would eventually move to Quartus Prime Standard v17.0.2 once we need the extra logic lock and partition features for functional safety, but for now we are using the Lite edition.

But when we compile with v17.0.2, the QSPI data exchange no longer works and we get intermittent bad data. We also tried an earlier working commit of our code that used standard SPI instead of QSPI and the same thing happened where it worked with 15.1.0, but not 17.0.2.

Is there some Quartus default setting that I need to change to make the compilation results more similar to what I get with v15.1.0?

I've attached the project .qsf file which remains the same whether I compile with v15.1.0 or v17.0.2, as well as the project .qdf file which was generated when I compiled with v17.0.2.

When I compare the assignment_defaults.qdf file from the Quartus 17.0.2 installation directory with the one generated by 17.0.2 in the project, there are only a couple of lines that are different:

Default settings:
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "\"\"" -section_id ?

Project .qdf setting:
set_global_assignment -name OCP_HW_EVAL -value OFF
(the EDA_EXTRA_ELAB_OPTION line from the default is missing in the project .qdf, so I'm assuming the default in the installation directory is being used?)

Are there any important settings that I would need to change to make the compilation more similar?

I'm a bit of a beginner, so any help would be appreciated.

Thanks,

Udell