Design works on Quartus 7.1 but not 4.2

Hi Maik:

I'm not a VHDL expert, I work in Verilog, however, I know both the VHDL and Verilog languages have changed since version 4.2.

Without seeing the code, it's hard to say, but one problem is you might be using new syntax that the older version of quartus doesn't understand. (IE: VHDL93 versus 200X).

It's a place to start anyway. At what point is it failing: Is it failing compile and synthesis, or is it completing, but just not functioning properly on the board?

If' it's failing compile, I but it's a syntax issue, and you'll have to re-write part of the cold to work with the VHDL93 standard.

Pete