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2. Use clocked process for manipulating signals and don't use variables at all.
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I wouldnt go this far - it depends on the OPs familiarity with VHDL. If you're a beginner, then yes. But if you understand what logic you expect from a given bit of code, variables can be a very neat way of wrapping up logic between registers and making your code more readable.
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3. Use only std_logic_vector and std_logic type in entity declaration. And in the design too.
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This is an OLD OLD throwback to when synthesis tools would only accept std_logic and std_logic_vector as ports. Now, I would recommend using any types you like internally, but at the top level make sure you have std_logics or std_logic array types (so signed/unsigned/sfixed/ufixed would be fine too). Using all types possible increases readability by removing all of the unneccesary type conversions.
What we dont see is the declaration of the bit8 and bit8H type. If they are custom arrays of std_logic, then you're making your life very difficult. If they are just suptypes of std_logic_vector, then crack on.
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