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Altera_Forum
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12 years ago

Design Stops Working When Modifying Unrelated Code

Hey there, I am experiencing some very strange behaviour with the FPGA implementation of my VHDL project. What I am designing is an implementation of an old 8-bit CPU. I have created...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Without this commented-out line flagVal stays zero (at least in provided code). At the end Q_DATA_ACC_ALU calculation happens in a different way than with the commented-out line.

I would write this one in a bit different way:

1. Use "normal" clock frequency and clock enable signal.

2. Use clocked process for manipulating signals and don't use variables at all.

3. Use only std_logic_vector and std_logic type in entity declaration. And in the design too.

4. Avoid bidirectional pins outside top level vhdl file.