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Altera_Forum's avatar
Altera_Forum
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12 years ago

Design Stops Working When Modifying Unrelated Code

Hey there, I am experiencing some very strange behaviour with the FPGA implementation of my VHDL project. What I am designing is an implementation of an old 8-bit CPU. I have created...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Could you post the commented-out code, that breaks your design?

I would suggest you start using SignalTap II integrated logic analyzer instead of running your design on extreme slow clock speed. Then check your counters in action and get some real information.