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Hi, I just tried a simple design and I couldn't reproduce this problem. I ran a 5 seed sweep in DSE searching for performance using highest effort level. DSE reported the best results at a point that wasn't base and I turned those best results into a new revision in the project using DSE's create-new-revision dialog. When I opened that new revision up in the Quartus II 7.2 GUI and ran it I saw the exact same timing results for the circuit, same worst-case slack for the clock, same failing paths, same utilization numbers, etc.
Sounds like this might be a problem specific to your circuit or use scenario. If you want to discuss it further just drop me an email. I'd be happy to help you try and figure out what's going on here.
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Yes I've just done the same thing as you, the compiled result in QII 7.2 is not same as in DSE. But I could get perfect matched results in QII 7.1 and it's DSE on the same project, so that make me think it's a new problem the new version software brings... Now I'm doing more test, thanks for your help.
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