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After I finished exploring and found a better timing result, I saved it as a new revision, opened it in QuartusII 7.2 and compile it, but the compiled timing result is not as the DSE reported! This problem makes the new v7.2's DSE almost useless, Now I'd rather roll back to v7.1, although v7.1 is full of bugs and crashes frequently, but at least it's DSE can give me a reliable result as it reported... But the most miserable thing is I can't found v7.1 web version's download link any more....
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Hi, I just tried a simple design and I couldn't reproduce this problem. I ran a 5 seed sweep in DSE searching for performance using highest effort level. DSE reported the best results at a point that wasn't base and I turned those best results into a new revision in the project using DSE's create-new-revision dialog. When I opened that new revision up in the Quartus II 7.2 GUI and ran it I saw the exact same timing results for the circuit, same worst-case slack for the clock, same failing paths, same utilization numbers, etc.
Sounds like this might be a problem specific to your circuit or use scenario. If you want to discuss it further just drop me an email. I'd be happy to help you try and figure out what's going on here.
Honored Contributor
