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Hi,
From Quartus manual about Design Space Explorer (DSE):
"In an exploration for best performance, DSE works on reducing the worst magnitude
slack, regardless of whether it is a hold slack or setup slack."
But I would like to instruct DSE to reduce setup time slack rather than hold time slack.
Is it possible to do this by ignore hold time constrain in SDC file?
Or other method?
Thanks.
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Hi,
unfortunately you have to solve both in order to make your design running. I would first
look to the holdtime violations, because they are often caused by design issue like gated gated etc. clock. After solving the holdtime you can run the DSE for setup optimizations.
Another solutions is to cut all paths with holdtime violations, but I would not recommend
it. I'm pretty sure that your design will not work properly.
Kind regards
GPK
Honored Contributor
