Design failed on board from time to time

You can use both edges in design inside fpga. I am sure Tricky means you cannot per process(register) and that is true obviosly in current technology.

Have you checked your reset operation. Does your failure/success occur per build or per power cycle or per some other change.

Remember timing tool will not check first set of registers for setup/hold or removal/recovery unless it has info on those paths(registered reset for example).