Altera_Forum
Honored Contributor
15 years ago"design does not contain any logic" But it has NAND logic and test bench!
Hi, everyone!
I have run into the problem that below for 3 days: --- Quote Start --- Error: Can't synthesize current design -- design does not contain any logic --- Quote End --- But the project included two files, one is testbench, and another is real source code. Why does such problem (that there are no logic) happen ? What setting or/and source code is wrong ? Please tell me what perhaps is! Thx! --- Quote Start --- module hogege; reg sw1, sw2; wire led; nandtest nandtest1 (sw1, sw2, led); initial begin sw1<= 0; sw2 <= 0; # 5 sw2 <= 1; end always begin # 10 sw1 <= ~sw1; end always begin # 16 sw2 <= ~sw2; end initial $monitor($stime, " sw1=%b sw2=%b led=%b", sw1, sw2, led); endmodule --- Quote End --- --- Quote Start --- //verilog1.v `timescale 1ns / 1ps module nandtest(input sw1, sw2, output led); assign led = ~(sw1 & sw2); // I think this is logic circuit endmodule --- Quote End ---