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Altera_Forum
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15 years ago

"design does not contain any logic" But it has NAND logic and test bench!

Hi, everyone! I have run into the problem that below for 3 days: --- Quote Start --- Error: Can't synthesize current design -- design does not contain any logic --- Quote End ---...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The testbench code is ignored by the Quartus compiler, because it doens't support timed statements (#<timeinterval>). As a result, no logic is synthesized. Use ModelSim Altera Edition with HDL testbenches or Vector Waveform Files with Quartus Simulator.