Design Assistant -> recommended flow

Hello,

Here are some useful references for you:

https://www.intel.com/content/www/us/en/products/docs/programmable/fpga-design-assistant-video.html

https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/design-assistant-design-rule-checking.html

https://www.intel.com/content/www/us/en/docs/programmable/683369/current/improving-quality-of-results-with-design.html

As far as I know it is not heavily time consuming during compilation.

As for which design rules you should always check, it depends on which part of the project you want to focus on, and what you have. For example if you are working on timing closure, you should check design rules under CLK and TMC categories, FLP could be helpful too. https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/design-assistant-rule-categories.html

If you are at the beginning of the project design phase, I'd suggest you start out by enabling the LNT and RES categories. Feel free to go through the design rules in the settings. As you go along you will know what you need to check.

Does this answer your question?

Regards,

Nurina