Occasional ContributorDescription of bidirectional signals and differential input signals in VHDL
As the title suggests, I have a question about describing bi-directional and differential input signals in VHDL. It would be helpful if you could teach me about the following points.
1) I would like to handle bi-directional signals. What is an example of VHDL description? What would be the grammatical problem with the following statement?
entity test is
port( BP : inout std_logic;
DIR : in std_logic;
OD : out std_logic )
end test;
architecture RTL of test is
signal a: std_logic;
signal i: std_logic;
begin
BD <= a when (dir = '1') else 'Z';
i <= BD;
OD,a outputs "some processing result"
end RTL;
2) As far as I searched the web for the VHDL description of the differential input signal, there was a description that the design was single-ended, the IO standard was set with the Pin Planner, and the P channel was assigned.
Also, if I assign it to the CLK pin, is that signal automatically connected to the global clock?
Please forgive me if it is hard to understand because of the text of machine translation.
Sorry for the long post, but thank you in advance.
Hi,
Check this VHDL: Bidirectional Bus sample design from Intel https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/v-bidir.html may be can help you out.
Thanks,
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
