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SKon1
Occasional Contributor
Occasional Contributor"derive_pll_clocks" doesn't create generated clocks properly
"derive_pll_clocks" doesn't create generated clocks properly Hello, In my Arria V design. I have a PLL with one input and 3 outputs. The input is 125 MHz. The outputs are as follows: 1. Output 0 ...
SKon1Occasional Contributor
Occasional ContributorThe design is attached,
The PLL of interest is named: "pll_ethernet_bridge" and it's located inside an hierarchy named: "ethernet_bridge".
After compiling, I opened Timequest and pressed "derive_pll_clocks".
I looked at the list of generated clocks and it seems like:
- clock output 0 was created
- clock output 1 wasn't created
- clock output 2 was created
I also ran "report_clocks" and looked in the list. The results where the same.
It seems like some kind of optimization is happening in the background.
