"derive_pll_clocks" doesn't create generated clocks properly

The design is attached,

The PLL of interest is named: "pll_ethernet_bridge" and it's located inside an hierarchy named: "ethernet_bridge".

After compiling, I opened Timequest and pressed "derive_pll_clocks".

I looked at the list of generated clocks and it seems like:

1. clock output 0 was created
2. clock output 1 wasn't created
3. clock output 2 was created

I also ran "report_clocks" and looked in the list. The results where the same.

It seems like some kind of optimization is happening in the background.