Demultiplexor Megafunction?

Will this be the proper way to make a 2bit 4 output demultiplexor?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux2_4 is
port (
      out0 : out  std_logic_vector(1 downto 0);   --output bit
      out1 : out std_logic_vector(1 downto 0);   --output bit
       out2 : out std_logic_vector(1 downto 0);   --output bit
      out3 : out std_logic_vector(1 downto 0);   --output bit
       sel : in std_logic_vector(1 downto 0);
       bitin : in  std_logic_vector(1 downto 0);   --input bit
     );
end demux2_4;
architecture Behavioral of demux2_4 is
begin
process(bitin,sel)
begin
out0 <= '00';
out1 <= '00';
out2 <= '00':
out3 <= '00';
case sel is
  when "00" => out0 <= bitin;
  when "01" => out1 <= bitin;
  when "10" => out2 <= bitin;
  when others => out3 <= bitin;
end case; 
end process;
end Behavioral;