It's fairly easy to create your own demux using HDL.
Quartus has an option to create a symbol from an HDL module, which you can then use in your design.
Here a small example in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
out0 : out std_logic; --output bit
out1 : out std_logic; --output bit
out2 : out std_logic; --output bit
out3 : out std_logic; --output bit
sel : in std_logic_vector(1 downto 0);
bitin : in std_logic --input bit
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(bitin,sel)
begin
out0 <= '0';
out1 <= '0';
out2 <= '0':
out3 <= '0';
case sel is
when "00" => out0 <= bitin;
when "01" => out1 <= bitin;
when "10" => out2 <= bitin;
when others => out3 <= bitin;
end case;
end process;
end Behavioral;