defparam issue vqm

1. Yes, as mentioned in the original question:

.vqm content (stratix10_fpga_a_mix.vqm):

rng4_sa_intg u_trng (
.ip_fpga_ringo_clk(free_running_48mhz_clk),
.clk_and_reset_p_pclk(rng_apb_clk),
...
.test_p_async_disable(GND)
);
defparam u_trng.APB_WIDTH=12;
// @1005:9418

2.Yes, as mentioned in the original question (I just added _stratix10 at the end compare to original stratix 3 version):

(set_global_assignment -name VQM_FILE ../../rng4_sa_intg/synplify/synthesis/rng4_sa_intg_stratix10.vqm)

content:

// VQM4.1+
module rng4_sa_intg (
ip_fpga_ringo_clk,
clk_and_reset_p_pclk,
...
test_p_async_disable
)
;

/* Synopsys
.origName=rng4_sa_intg
.langParams="APB_WIDTH"
APB_WIDTH=12
*/
input ip_fpga_ringo_clk ;

...

3. Will try now. Edit: Same result with version T-2022.09