From the error message, the issue is probably due Quartus not recognizing the parameter APB_WIDTH in the instantiation of the rng4_sa_intg module.
Few steps to narrow down and solve it:
1. Check the syntax of the instantiation in stratix10_fpga_a_mix.vqm and ensure that the parameter is spelled correctly and in the correct location. It should be in the parentheses following the module name:
rng4_sa_intg u_trng (
.ip_fpga_ringo_clk(free_running_48mhz_clk),
.clk_and_reset_p_pclk(rng_apb_clk),
...
);
defparam u_trng.APB_WIDTH=12;
2. Ensure that the rng4_sa_intg module is correctly included in the Quartus project
3. Try generating a new .vqm file with the latest version of Synplify and see if the issue persists.