Definition of Clock setup slack

Yes, it's virtual. It's generally:

Tco of the previous device + PCB delay - (PCB clock skew)

So if the setupr relationship was 10ns between the clocks, the Tco of the external device is 4ns, the PCB delay is 0.5ns, and the clock delay to the FPGA is 200ps longer than the delay to the upstream device, then your -max input delay is 4.3ns. That means inside the FPGA your data can be 5.7ns long. You also want to do the -min calculations.

Note that there are other ways to do the board level clock skew. You could either shift the clock edges(not recommended) or use set_clock_latency, but I've found most people just roll it into their input/output delay constraints, and that works best.

And don't forget you can use equations. For example, if the data is coming from an ADC, put something like:

set adc_tco_max 4.0 ;# Found on page 4-14 of ADC datasheet

set adc_pcb_max 0.5

set adc_fpga_max_skew .02

set adc_delay_max [expr $adc_tco_max + $adc_pcb_max - $adc_fpga_max_skew]

set_input_delay -clock adc_clk_ext -max $adc_delay_max [get_ports adc_inputs*]

I'm a huge fan of this because it documents what you've done. Otherwise someone else gets the constraints(maybe years down the line) and has no idea how they were calculated, how a board re-spin would affect them, etc., but this way it's all there.