Definition of Clock setup slack

Thank you very much indeed, Rysc.

You made clear about the source and destination registers.

When you say that "the source register is the one outside of the FPGA that drives data into that port", I suppose that the source register is a virtual register. It does NOT actually exist and is imagined as a register only for timing calculation purpose. There is no way to find this info from any Altera documentation.

In this case, I think that Input Maximum Delay of Pin is the PCB trace delay from the source register to the pin.