Definition of Clock setup slack

There are two registers when doing timing from an input port to an internal register(there are two registers on all calculations, really). The destination register is the one in the FPGA, but the source register is the one outside of the FPGA that drives data into that port.

When you add a constraint "set_input_delay ..." you're automatically saying there is an external register driving in on whatever port you specify. The -clock option specified what clock drives that external register. Note that it is recommended to create a virtual clock. So, for example, if I have a clock coming into the FPGA, maybe going through a PLL, and driving my input register in the FPGA, and let's say that clock is 10ns, then I might do something like:

create_clock -period 10.0 -name ext_clock

set_input_delay -clock ext_clock -max# .### [get_ports datain*]

set_input_delay -clock ext_clock -min# .### [get_ports datain*]

Note that the created clock is not assigned to anything, making it virutal, and I use it to clock the external register.

Now we have the classic register to register path described. Assuming the clock in the FPGA is 10ns, we have a setup relationship of 10ns and a hold relationship of 0ns.

Hopefully that gets you started, but I find looking at the actual constraints and analyzing the TimeQuest reports a lot more productive than looking at equations, because once you figure them out, you then need to see how that is done in TimeQuest.