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Altera_Forum
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14 years ago

Defining Flops with Async Set & Reset

Hi, I have been trying to synthesize a flop with both a asynchronous set and a reset input on a Cyclone V using Quartus 11.1sp2. I have not been able to. I use always @(posedge clk or...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks for the reply. Yes, the set_n line had a typo.

As for the answer the application has really both set and reset. I was using the asynchronous fifo as described in the sunburst paper from 2002 http://www.sunburst-design.com/papers/cummingssnug2002sj_fifo2.pdf

Anyways in this application the two never occur at the same time and if the reset is held long enough then there should be no chances of glitches. So it will probably work.

Thanks for the warning though on how the Cyclone FPGAs implement set/reset flops.

-G