Altera_ForumHonored Contributor13 years agoDefining Flops with Async Set & Reset Hi, I have been trying to synthesize a flop with both a asynchronous set and a reset input on a Cyclone V using Quartus 11.1sp2. I have not been able to. I use always @(posedge clk or...Show More
Recent DiscussionsCompilation error due to LPDDR5 I/O standard settingQuartus did not startQuartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"Issues with downloadingError (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10