Defining Flops with Async Set & Reset

I guess you mean

else if (!set_n) q <= 1'b1;

Then you get a compiler warning

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Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

Warning (13310): Register "q~reg0" is converted into an equivalent circuit using register "q~reg0_emulated" and latch "q~reg0latch"

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It's a question of FPGA hardware properties, not software behaviour.

Starting with Cyclone II, asynchronous preset and load of FPGA core registers have been abandoned, the registers have only an asynchronous clear since then. If you need asynchronous load, or both reset and preset of registers, the function needs to be emulated by additional logic cells and latches (the latter implemented as combinational loops).

The below gate level schematic shows the involved logic. It's rather obvious, why it will be "glitchy" and slower than a basic register. The priority of rst_n should be observed according to the RTL schematic, however.

P.S.: There's detailed help on the above quoted warning available

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CAUSE: One or more registers in the design have one of the following conditions:

•The register has both a preset and a clear signal.

•The register has a preset signal but does not have a clear signal, and Analysis & Synthesis turned off the NOT Gate Push-Back logic option.

•The register has an asynchronous load and corresponding data signal.

The current device family does not support any of these conditions. As a result, Analysis & Synthesis converts the register to equivalent circuits with a latch, a register and logic, and the resulting register powers-up to an undefined state (X). In addition to that, DEV_CLRn places the register in an undefined state, and the resulting circuit is prone to glitches because the there are different paths from the asynchronous signals to the output of the logic representing the register. Since these paths have different delays, glitches can occur, especially if the asynchronous signals are coming from combinational logic, or if the register is feeding combinational logic. See submessages for details.

ACTION: No action is required. If you want to prevent glitches, put KEEP attributes on the asynchronous signals that feeds the register, and on the register itself. This action is necessary only if the asynchronous signals come from combinational logic or if the register feeds combinational logic. Make sure that you perform timing simulation to verify that no unexpected glitches occur.

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