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Altera_Forum
Honored Contributor
12 years agoI have another question please :
I have multiple clock domains in my design. The data to be processed is written to registers that are working on clock1. The data processing elements are working on clock2. The two clocks are unrelated. I do not need to add any signal synchronizers as I'm sure that domain/clock2 will read the data registers @ domain/clock1 after a long time so that the register contents can be assumed static. I do not need the tool to perform timing analysis on the paths crossing the domains so, I should set false paths between the two domain. How can I set all paths between the two domains as false paths ? If I need in another case to set false paths between specific registers -the registers may be in different hierarchies- how can I do that ?