Define internal signal as a base clock?

Followup:

With all the 'cut timing path' assignments, I no longer get setup time errors, and the Fmax for my design is reasonable.

But...

I still get Hold time violations for a lot of the registers which are clocked by clk_logic, which is odd because I've forced that signal to use one of the global clock nets. Skew between registers really shouldn't be a problem - and looking at the deeper analysis of the paths that are failing, it actually isn't.

What seems to be happening is this:

In the real code, as well as a multiplexer to select between input clocks, I also have a programmable divider associated with each clock input. So, there are multiple paths possible between each clock pin and clk_logic, depending on how the divider is programmed.

The timing analyser is - erroneously, I think - considering the shortest possible path through that divider and the longest possible, and coming to the conclusion that there's a skew problem. It doesn't seem to notice that, whatever the path through the divider, the source and destination registers are in fact driven off the exact same global signal.

I could just ignore the hold time violation errors, but there's a lot of them and it's always possible that there's a real problem hiding amongst them. The Fitter will also be misguided.

Driving my derived clocks out to external pins and back in again is starting to feel like an increasingly attractive option, but it seems a really ugly hack. If it pushes me over into a bigger package then I'll be upset!

Any ideas please guys?