--- Quote Start ---
I think it's also possible with Classic Timing Analyzer to cut the "false path" from clk_cpu to clk_logic domain. I achieved this through
cut timing path assignments as suggested in Quartus Handbook, chapter Classical Timing Analyzer, timing execptions.
I first tried -from clk_mux_setting* -to *, but that didn't work. For some reason, Timing Analyzer needs the assignment for each bit of clk_mux_setting[] separately. See below how the assignment was entered in assignment editor. There are also other possibilties, e. g. cut clk_cpu to result, but this would probably require a lot of signals to be handled explicitely.
--- Quote End ---
I like this idea a lot. Many of the registers in the design are effectively 'set and forget', so cutting the timing path from these registers to everything else makes perfect logical sense.
So...
This morning I tried putting all the clock control registers into an Assignment Group, and set up an assignment:
From: regs_that_control_clocks To: * Cut Timing Path On Enabled
...and it didn't work :( My design's Fmax remains low, and if I use 'Advanced List Paths' to show me details of the slowest path on the chip, it goes via one of my mux control registers.
Then I remembered an issue I've seen before, which IIRC came in with Quartus 6.0 - the same time, I think, as when 'Time Groups' got renamed to 'Assignment Groups'.
Quite simply, assignments using Assignment Groups get ignored.
To test this theory, I tried setting up a whole bunch of separate assignments, each of the form:
From: clk_mux[1] To: * Cut Timing Path On Enabled
...and now it works fine :D
The downside is, of course, I end up with lots more assignments, which will be hard to manage.
Has anyone else come across this problem with Assignment Groups?
Honored Contributor
