Define internal signal as a base clock?

Hello,

regarding the multiplexer-in-LUT, if have searched for related statements in Altera documents. I found only a statement yet, that says, no glitches should be expected.

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problem

Will the output of a 4-to-1 mulitplexer implemented in an Altera FPGAs glitch while the select lines are stable?

solution

No. If the select lines are stable while the other three inputs are changing, the silicon is designed such that the LUT output will not glitch. However, glitches may occur when the select lines are changing. http://www.altera.com/support/kdb/solutions/rd04202001_2747.html

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In contrast, for different logic function than utilized in a multiplexer, a change of one input can cause an unexpected glitch due to differences in delay:

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problem

Can a single FLEX look-up table (LUT) cause a glitch with one input switching?

solution

If a function fits into one LUT, there will not be a glitch on the output when any single input toggles. For example, a 2-to-1 multiplexer can be represented as: q = (a & sel)# (b & !sel) If a and b are both 1 and sel switches from 1 to 0, differences in the delay between the two gates could result in a 0 glitch on the output if the design were really implemented in gates. However, the FLEX LUT is designed so that this function will not result in a glitch on the output. A function composed of multiple LUTs may cause glitches on a combinatorial output because the delays between the LUTs may be different. To avoid glitches when using multiple LUTs, register the output of the combinatorial circuit. http://www.altera.com/support/kdb/solutions/789.html

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In my view, there is a clear structural difference between the two cases discussed here, which allows to distinguish, why in the latter case glitches may occur but not in the first. Unless other results are known, I see a confirmation of my previous assumption regarding muxes in LUT. When the above restriction is considered, also chained muxes would be safe, except for the additional clock delay, which is however under Timing Analyzers observation.

On the other hand, I agree, if LUT operation would be similar to an asynchronous RAM, then glitches should be expected. So I hope, the quoted Altera statement is fully correct.

Regarding "Cut Timing Path"

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There was a case in the past where the behavior was changed

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I have no reason to contradict, but I'm interested to know the details.

Regards,

Frank