Define internal signal as a base clock?

Hello,

I think it's also possible with Classic Timing Analyzer to cut the "false path" from clk_cpu to clk_logic domain. I achieved this through cut timing path assignments as suggested in Quartus Handbook, chapter Classical Timing Analyzer, timing execptions.

I first tried -from clk_mux_setting* -to *, but that didn't work. For some reason, Timing Analyzer needs the assignment for each bit of clk_mux_setting[] separately. See below how the assignment was entered in assignment editor. There are also other possibilties, e. g. cut clk_cpu to result, but this would probably require a lot of signals to be handled explicitely.

The said assignment declares clk_mux_setting effectively a static value that is unrelated to cpu_clk, accepting to "get glitches in clk_logic when the CPU changes settings", as been said.

Regarding the multiplexer issue raised by Brad, I think, this shouldn't cause any trouble as long as clk_mux_setting is constant, although the multiplexer is decomposed to multiple cascaded LUT levels. My argument is, that for a given combination of clk_mux_setting the logic is such, that the multiplexer output doesn't depend on any other clock input than the selected one. But I'm not absolutely sure of this conclusion, so if you can give an example suggesting this might be different, I would think anew.

Not as important, but I wouldn't expect the mixed process clocks to have any effect in synthesis. But they should be clearly separated for code clarity.

Regards,

Frank