Define internal signal as a base clock?

See my posts in the thread at http://www.alteraforum.com/forum/showthread.php?t=754 for things you need to be aware of if you are going to drive a clock with logic resources. The things I say in that thread about divided-down clocks also apply to clocks driven by a multiplexer.

Some device families have clock control blocks, which are dedicated silicon configured with the altclkctrl megafunction to perform functions like clock gating and clock multiplexing. For a clock multiplexer implemented in logic resources instead of in a clock control block, make sure that each LUT or ALUT has at most one input toggling at a given time. There is more about that below. If your mux has a LUT with more than one clock input toggling, the output can glitch even while the select input is constantly selecting only one of those clock inputs. You can use "keep" synthesis attributes, instantiate LCELL primitives, or use WYSIWYG primitives to control how the muxing logic is broken down into individual LUTs or ALUTs.

The Classic Timing Analyzer is limited in its support for clock muxes. It would be best to use TimeQuest.

I doubt that your process with two clocks in the sensitivity list will synthesize correctly. Each process should have a single clock. When using metastability registers to cross between clock domains, the registers for each domain should be in their own process.

Here is what someone else wrote about having at most one input to the mux toggle at once:

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Make sure each clock is gated prior to the mux to prevent glitches on the output. So:

clkA ----|

AND --- LCELL

cntrlA ---|

clkB ----|

AND----LCELL

cntrlB ---|

The outputs of the LCELLs will feed the mux, and only the active clock will be toggling when it hits the mux as it will be the only enabled clock. The mapper will collapse the “extra” LCELL into the AND, but will not collapse the AND functionality into the MUX which is what you want.

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