I am assuming this is a fairly simple problem, but I'm spending way too much time trying to fix it. I have a PLL clock in Quartus that I am trying to output directly to a D2A chip. When I specify this PLL as an output, I get the warning that my PLL feeds an output pin via global clocks and that I should be using PLL dedicated clock outputs. I've noticed a lot of discussion about using dedicated clock lines, but I don't know how to even specify this. Any help is appreciated!

There is a pin(or pair of lvds pins) that can be used as a dedicated pll output for each pll. The pin out file will tell you which pins these are for each package. All you need to do is assign the relevant pin to the signal connected to the pll output the same way you'd assign any signal to a pin location.

Are you saying that I am required to use only a specific set of pins on the device? In other words, I can't just specify any output pin to do this?

That's right, each device has one dedicated pin that can be associated with each pll. This pin is hardwired within the fpga and cannot be assigned to any other pin. However the output of the pll can be routed to any io pin through a clock net it's just that the delay will be longer. The pins are defined in the pin file for each device as pll#_out in the optional functions column.

The device handbook is another place that documents which dedicated PLL device pins go with each PLL. It might be OK for your design to use a nondedicated PLL output pin. Besides the delay from the PLL to the pin, the jitter is affected. I expect you got a warning like this: --- Quote Start --- Warning: PLL "my_pll:pll|altpll:altpll_component|pll" output port clk[1] feeds output pin "pll_output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance --- Quote End --- If your DAC can tolerate more jitter than is in the FPGA device handbook spec for the PLL output, then you might be OK with the present pin-out. The help for that warning: --- Quote Start --- PLL "<name>" output port <name> feeds output pin "<name>" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -------------------------------------------------------------------------------- CAUSE: The specified clock port of the specified PLL feeds an output pin via non-dedicated routing. This may cause jitter performance to degrade due to noise from multiple switching design elements. Use PLL dedicated clock outputs to ensure jitter performance. ACTION: To avoid receiving this message, modify the design so that the specified clock ports of the specified PLL do not feed an output pin or use the PLL dedicated clock outputs to feed an output pin for better jitter performance. --- Quote End ---

Thanks to both of you for your help.

Dedicated Clock Pin Out | Altera Community

15 Replies

Altera_Forum
Honored Contributor
15 years ago
Ardni I have the same problem on CycloneIII.
I explicitly assign to PLL1 and I explicitly output from a PLL1 dedicated output pin. Still I get that warning. Any clues ?
Altera_Forum
Honored Contributor
14 years ago
All you have not get the essential of the PLL dedicated output.
You should look into the handbook carefully so that you will know why even if you routed the PLL output to the PLL dedicated output, but still get the warning!
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
All you have not get the essential of the PLL dedicated output.
You should look into the handbook carefully so that you will know why even if you routed the PLL output to the PLL dedicated output, but still get the warning!
--- Quote End ---

I RTFM and still don't get it--thanks for the help. I'm pretty sure I understand *what* I need to do and why, I've just wasted three days trying to figure out *how* to make Quartus do what I want it to do with respect to PLL outputs on a Stratix-IV device.

I want a PLL to drive an output clock (yes, the specific pin associated with that PLL's output clock) as well as connect to a regional/global clock net to drive the reference clock on a digital synthesizer. I simply can't get all of the jitter warnings to go away--why can't I connect a PLL to a dedicated output pin (c0) as well as a global clock (c1)?

I'll slog through the manuals once more, but this isn't helping my blood pressure. This wasn't that hard on Xilinx. :/
Altera_Forum
Honored Contributor
13 years ago
If you are feeding both internal logic and want it to go to an output pin you will have to have two outputs from the PLL. One that goes ONLY to the output pin and the other feed the internal network. This will get rid of the warning.

Similarly when you try to feed a PLL from a pin. Don't use that clock from the pin for anything else, but the PLL input. If you need that frequency just generate a x1 clock in the PLL and use that.

Hope that helped

/Boris
Altera_Forum
Honored Contributor
11 years ago
Watch out for cascaded counters! If the desired output clock, the one you want to drive out on the dedicated output pin, has a frequency that is too low, the Quartus ALTPLL MegaWizard will use counter cascading to generate it. You will see a note like this:

Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_2)

But the output from counter C1 cannot drive the dedicated pin, so then Quartus gives the very misleading warning:

Warning (15064): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "test_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

There is NO MENTION of cascaded counters as a possible reason for it. I got this for a Cyclone IV device; my test design had only one input (a 40MHz clock) and one output (200kHz) with no pin assignments. One quick way to figure out if your PLL will require cascaded counters is to scroll down in the description window of c0 output clock in the ALTPLL MegaWizard. Here you will find the various settings required for the C0 output. If you see a section titled "Cascade tap settings: (For c0)" the output will not be on c0 and it will not be able to directly drive the PLL output pin.

If you need clock this slow, perhaps you don't care about the jitter and can ignore the warning. If you do care about the jitter, then a better implementation would be to use a higher frequency clock to create a registered version of the output clock.

I hope Altera will recognize this and add it to the possible causes of the warning. Or better yet, make a new warning specifically for this problem.

If they had to pick one output, I wonder why the Altera chip designers chose the c0 output to drive the dedicated pin, instead of say c5, which would have allowed cascading to be used with the dedicated output.

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Dedicated Clock Pin Out

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