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All you have not get the essential of the PLL dedicated output.
You should look into the handbook carefully so that you will know why even if you routed the PLL output to the PLL dedicated output, but still get the warning!
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I RTFM and still don't get it--thanks for the help. I'm pretty sure I understand *what* I need to do and why, I've just wasted three days trying to figure out *how* to make Quartus do what I want it to do with respect to PLL outputs on a Stratix-IV device.
I want a PLL to drive an output clock (yes, the specific pin associated with that PLL's output clock) as well as connect to a regional/global clock net to drive the reference clock on a digital synthesizer. I simply can't get all of the jitter warnings to go away--why can't I connect a PLL to a dedicated output pin (c0) as well as a global clock (c1)?
I'll slog through the manuals once more, but this isn't helping my blood pressure. This wasn't that hard on Xilinx. :/
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